CN101188560A - Method and device for dynamically detecting forward capability - Google Patents
Method and device for dynamically detecting forward capability Download PDFInfo
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- CN101188560A CN101188560A CNA2007101798112A CN200710179811A CN101188560A CN 101188560 A CN101188560 A CN 101188560A CN A2007101798112 A CNA2007101798112 A CN A2007101798112A CN 200710179811 A CN200710179811 A CN 200710179811A CN 101188560 A CN101188560 A CN 101188560A
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Abstract
The invention discloses a method and a device for realizing the transmitting ability dynamical detection. In the invention, through detecting memory status identification state of memory spaces corresponding to the side of a CPU, current treatment ability of the CPU can be detected, thereby the transmitting ability of the CPU can be acquired. The outgoing interface CPU transmitting ability is noticed to each corresponding ingress interface, and the outgoing interface CPU transmitting ability is used by ingress interfaces to determine message flow being sent to the outgoing interface from the ingress interfaces, thereby realizing effectively the flow control among plates, ensuring that the sum of the message flow of all corresponding ingress interfaces does not go beyond the CPU transmitting ability of the outgoing interface, and providing the guarantee for preventing the file bag from being lost at the outgoing interface and avoiding the waste of the exchange network flow. Furthermore, while the memory status identification of the used state at the side of the CPU is less than a certain number, ingress interfaces can be noticed to increase the transmitting message flow to prevent the waste of the transmitting ability of the Cpu of the outgoing interface.
Description
Technical field
The present invention relates to the flow control technique in the transfer of data, the particularly a kind of method of transfer capability detection of dynamic, a kind of device of realizing the transfer capability detection of dynamic realized.
Background technology
In the existing distributed route system based on the switching network technology, comprise a plurality of routing devices, each routing device all links to each other with other routing devices by switching network.
Wherein, each routing device all can be used as the incoming interface of distributed route system, reception is from the message of system outside, and is transferred to other routing devices as outgoing interface by the switching network in the system, by the routing device as outgoing interface message is forwarded to outside the system again.
Fig. 1 is the exemplary block diagram of existing distributed route system.As shown in Figure 1, comprise 3 routing devices in this system, i.e. interface board LPU_a, interface board LPU_b, interface board LPU_c, each interface board all link to each other with other 2 interface boards by exchange (Switch) chip, and the Switch chip is regarded switching network as.Wherein, LPU_a and LPU_b are as the incoming interface plate, to send to LPU_c as the outgoing interface plate by the Switch chip of net in return from the message outside the system, LPU_c will be forwarded to from the message of LPU_a and LPU_b outside the system, the flow direction of unidirectional arrow curve representation message flow.
In the said system, include a field programmable gate array (FPGA) and a CPU (CPU) that is used for the message forwarding that is used for flow control between plate in each interface board.Adopt system's packet interface (SPI4) of fourth stage data rate between FPGA and the CPU.
Show as Fig. 2, for LPU_c as the outgoing interface plate, the message that FIFO_1 among its FPGA receives from LPU_a and LPU_b carries out buffer memory, then, FPGA is cached to FIFO_2 again with the message to be sent of buffer memory among the FIFO_1, is mail to the FIFO_3 of this SPI4 interface among the CPU by the SPI4 interface by FIFO_2.
Normal conditions, the CPU side of interface board adopt buffer description (BD) mechanism to handle the message that receives from FPGA usually, and each BD represents different memory headroom store statuss.The detailed process that CPU handles message based on BD mechanism among the outgoing interface plate LPU_c comprises:
A, CPU side SPI4 interface hardware is as shown in Figure 2 inquired about idle BD, and after applying for the data/address bus right to occupation, to be buffered in the memory headroom that message to be sent among the FIFO_3 is sent to idle BD correspondence successively, be that the message direct memory to be sent that the SPI4 interface hardware will be buffered among the FIFO_3 successively inserts (DMA) memory headroom to idle BD appointment, rewrite the information of this free time BD then, for example write information such as message length, and this BD is set to use state.
B, the SPI4 interface hardware processing kernel (not shown) in CPU produces interrupts.
Processing kernel among c, the CPU is after the response interface hardware interrupts, and knowing has message to need to handle, and notifies its inside to be used to handle the task of message.
When the processing kernel among d, the CPU is used for the task of message processing in execution, the message that receives is carried out respective handling, and after finishing dealing with, the pairing BD of the memory headroom that this message takies is set to idle condition, promptly discharges BD.
Based on above-mentioned flow process, outgoing interface plate LPU_c has realized that its CPU is to message forwarding.
Suppose among the CPU among the LPU_c that the disposal ability of handling kernel has only 1Gbps, and the message flow of the current transmission of FPGA is much larger than 1Gbps (message flow of the current transmission of FPGA among the LPU_c equals the message flow sum from LPU_a and LPU_b), then FIFO_3 will reach almost full (AlmostFull) state very soon among the CPU, thereby produce the back-pressure signal by the SPI4 interface, make FPGA suspend and send message flow.
Like this, FPGA suspends after CPU sends message flow, because FIFO_1 still receives the message from LPU_a and LPU_b, makes the FIFO_2 of SPI4 interface side will also reach the AlmostFull state within a certain period of time.After FIFO_2 reached the AlmostFull state, the message among the FIFO_1 then can't re-send to FIFO_2, thereby made FIFO_1 overflow, and the result of overflowing is exactly a packet loss between plate, and promptly LPU_c loses the message from LPU_a and LPU_b.
As seen, in the existing distributed route system based on the switching network technology, owing to can't know the CPU transfer capability of outgoing interface plate, thereby the message flow sum that can't guarantee all corresponding incoming interfaces can not exceed the CPU transfer capability of (perhaps can not exceed for a long time) outgoing interface, also just can't avoid outgoing interface place packet loss, thereby cause the waste of switching network flow.
Summary of the invention
In view of this, the invention provides a kind of method of transfer capability detection of dynamic, a kind of device and a kind of system that realizes the transfer capability detection of dynamic that realizes the transfer capability detection of dynamic of realizing, can provide safeguard for avoiding outgoing interface place packet loss.
A kind of method that realizes the transfer capability detection of dynamic provided by the invention is applied in the distributed route system, and for each memory headroom in the outgoing interface board memory is provided with corresponding store status sign respectively, this method comprises:
After outgoing interface plate CPU receives message, this message is stored in idle store status identifies in the pairing memory headroom, and this store status sign is set to use state; CPU is after the processing of finishing message, and the pairing store status sign of memory headroom of storing this message is set to idle condition;
Whether detection reaches default upper limit threshold with the store status sign sum of state;
When reaching default upper limit threshold with the store status of state sign sum, determine the transfer capability deficiency of this CPU.
Store status sign is set to carry out once described detection and to identify the total default upper limit threshold that whether reaches with the store status of state with after the state at every turn.
After the transfer capability deficiency of determining this CPU, this method further comprises:
Send the plate inner control message of this CPU transfer capability deficiency of expression to the field programmable gate array FPGA of this CPU place outgoing interface plate;
The FPGA of this CPU place outgoing interface plate controls message between the plate of this CPU transfer capability deficiency of incoming interface plate transmission expression of correspondence.
Before described FPGA to this CPU place outgoing interface plate sent the plate inner control message of this CPU transfer capability deficiency of expression, this method further comprised:
Judge whether to send to the FPGA of this CPU place outgoing interface plate the plate inner control message of this CPU transfer capability deficiency of described expression, if no, then carry out the described plate inner control message that sends this CPU transfer capability deficiency of expression to the FPGA of this CPU place outgoing interface plate.
After described incoming interface plate to correspondence sent and controls message between the plate of representing this CPU transfer capability deficiency, this method further comprised:
The incoming interface plate stops to send message or reducing the message flow that sends to described outgoing interface plate to described outgoing interface plate.
The store status sign of each correspondence is set to after the idle condition, and this method further comprises:
Detect interface board CPU side and whether reduce to default lower threshold with the store status sign sum of state;
When reducing to default lower threshold with the store status sign sum of state, determine that this CPU has enough transfer capabilitys.
After definite this CPU had enough transfer capabilitys, this method further comprised:
Send this CPU of expression to the FPGA of this CPU place outgoing interface plate and transmit the plate inner control message that enough transfer capabilitys are arranged;
The FPGA of this CPU place outgoing interface plate sends this CPU of expression and has to the incoming interface plate of correspondence between the plate of enough transfer capabilitys and controls message.
Before described FPGA to this CPU place outgoing interface plate sent and represents that this CPU forwarding has the plate inner control message of enough transfer capabilitys, this method further comprised:
Judge whether to send the plate inner control message of representing that this CPU transmits enough transfer capabilitys to the FPGA of this CPU place outgoing interface plate, if no, then carrying out described FPGA to this CPU place outgoing interface plate sent and represented that this CPU had the plate inner control message of enough transfer capabilitys.
Described incoming interface plate to correspondence sends this CPU of expression and has between the plate of enough transfer capabilitys after the control message, and this method further comprises:
The incoming interface plate continues to send message or increase the message flow that sends to described outgoing interface plate to described outgoing interface plate.
Described upper limit threshold smaller or equal to total store status sign quantity and message arrive the opposite end in the time the pairing store status in required maximum memory space identify the poor of quantity.
Described lower threshold arrives the opposite end maximum message segment quantity that CPU can handle in the time more than or equal to message.
Described store status is designated buffer description BD.
A kind of device of realizing the transfer capability detection of dynamic provided by the invention is used for the outgoing interface of distributed route system, and this device comprises: internal memory and CPU, wherein,
The respectively corresponding different storage states sign of each memory headroom in the described internal memory;
After described CPU receives message, this message is stored in idle store status identifies in the pairing memory headroom, and this store status sign is set to use state; After the processing of finishing message, the pairing store status sign of memory headroom of storing this message is set to idle condition;
Whether described CPU detection reaches default upper limit threshold with the store status sign sum of state; When reaching default upper limit threshold with the store status of state sign sum, determine the transfer capability deficiency of this CPU.
Described CPU carries out described detection and whether reaches default upper limit threshold with the store status sign sum of state after the store status sign is set to state.
This device further comprises: on-site programmable gate array FPGA;
Described CPU further sends the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA after determining its transfer capability deficiency;
Described FPGA controls message between the plate of the described CPU transfer capability deficiency of outside incoming interface transmission expression of correspondence.
Described CPU sends before the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA, further judge whether to send to described FPGA the plate inner control message of this CPU transfer capability deficiency of described expression, if no, then carry out the described plate inner control message that sends this CPU transfer capability deficiency of expression to FPGA.
The store status sign of described CPU correspondence is set to after the idle condition, further detects interface board CPU side and whether reduces to default lower threshold with the store status sign sum of state; When reducing to default lower threshold with the store status sign sum of state, determine that this CPU has enough transfer capabilitys.
Described CPU further sends this CPU of expression to described FPGA and transmits the plate inner control message that enough transfer capabilitys are arranged after definite this CPU has enough transfer capabilitys;
Described FPGA sends the described CPU of expression and has to the outside incoming interface plate of correspondence between the plate of enough transfer capabilitys and controls message.
Described CPU is before sending the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA, further judge whether to send the plate inner control message of representing this CPU transfer capability deficiency to described FPGA, represent that this CPU has the plate inner control message of enough transfer capabilitys if no, then carry out described the transmission to described FPGA.
Described upper limit threshold smaller or equal to total store status sign quantity and message arrive the opposite end in the time the pairing store status in required maximum memory space identify the poor of quantity.
Described lower threshold arrives the opposite end maximum message segment quantity that CPU can handle in the time more than or equal to message.
Described store status is designated buffer description BD.
As seen from the above technical solution, the present invention can detect the current disposal ability of this CPU by the store status identification-state of surveying corresponding each memory headroom of CPU side, thereby can obtain the transfer capability of this CPU.Like this, with each corresponding incoming interface of outgoing interface CPU transfer capability notice, determine that in order to each incoming interface self is to message flow that this outgoing interface sent, with Flow Control between effective realization plate, guarantee that the message flow sum of all corresponding incoming interfaces can not exceed the CPU transfer capability of outgoing interface, thereby, avoid the waste of switching network flow for avoiding outgoing interface place packet loss to provide safeguard.
And, when the CPU side is less than some with the store status of state sign, also can notifies each corresponding incoming interface to increase the message total amount of transmission, thereby can avoid the waste of outgoing interface CPU transfer capability.
Description of drawings
Fig. 1 is the exemplary block diagram of existing distributed route system.
Fig. 2 is the structural representation of the interface board in the existing distributed route system.
Fig. 3 is for realizing the exemplary process diagram of the method for transfer capability detection of dynamic among the present invention.
Fig. 4 is a method flow schematic diagram of realizing the transfer capability detection of dynamic in the embodiment of the invention.
Fig. 5 is an apparatus structure schematic diagram of realizing the transfer capability detection of dynamic in the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
It among the present invention each memory headroom in the outgoing interface board memory, corresponding store status sign is set respectively, and know the state of each memory headroom by surveying each store status sign of CPU side, thus detect the current disposal ability of CPU, thus the transfer capability of this CPU obtained.
Generally, CPU all adopts BD mechanism to realize management to memory headroom, and therefore, below to be designated BD with store status be example, and technical scheme of the present invention is elaborated.
Fig. 3 is for realizing the exemplary process diagram of the method for transfer capability detection of dynamic among the present invention.This method can be applicable in the distributed route system, and as shown in Figure 3, this method comprises:
Step 302 when reaching default upper limit threshold with the BD sum of state, is determined the transfer capability deficiency of this CPU.
So far, this flow process finishes.
Certainly, can also detect interface board CPU side in the above-mentioned flow process and whether reduce to default lower threshold with the BD sum of state, and when reducing to default lower threshold with the BD sum of state, determine that this CPU has enough transfer capabilitys.
Like this, according to the outgoing interface CPU transfer capability of determining, each incoming interface that the control message notifying correspondence of enough transfer capabilitys is arranged by expression CPU transfer capability deficiency or expression CPU, reduce or increase the message flow that sends to this outgoing interface, thereby Flow Control between the realization plate, can not exceed the CPU transfer capability of outgoing interface with the message flow sum that guarantees all corresponding incoming interfaces, thereby avoid outgoing interface place packet loss, avoid the waste of switching network flow.
Below, in conjunction with specific embodiments the technical scheme among the present invention is further specified.
In order the transfer capability of outgoing interface CPU to be notified to each incoming interface, to the invention provides two kinds of plate inner control message CBUSY and n_CBUSY, and control message FBUSY and n_FBUSY between two kinds of plates.
Wherein, CBUSY represents that CPU transfer capability deficiency, n_CBUSY represent that CPU has enough transfer capabilitys.Thereby after reaching default upper limit threshold with the BD sum and determining interface CPU transfer capability deficiency, CPU sends the CBUSY message to FPGA; Thereby when reaching default lower threshold and determine that the CPU transfer capability has been recovered with the BD sum, send the n_CBUSY message to FPGA.
Generally speaking, CPU message in the plate that FPGA sends all can attach a control head that is used to store control information, has comprised for example information such as the purpose plate ID of this message, message priority in this control head, also has idle free space simultaneously.Like this, the represented information of plate inner control message CBUSY among the present invention and n_CBUSY can only take two bits in the control head, and the total length of this plate inner control message only need be set to the minimum message length between CPU and the FPGA.
FBUSY represents that CPU transfer capability deficiency, the n_FBUSY of this plate represent that the CPU of this plate has enough transfer capabilitys.
FPGA need be converted to control message FBUSY or n_FBUSY between corresponding plate, so that the FPGA of the incoming interface plate of this FPGA place outgoing interface plate correspondence can discern behind the plate inner control message CBUSY or n_CBUSY that the CPU that receives its place outgoing interface plate sends.
Same, control message FBUSY and the represented information of n_FBUSY also can only take two bits in the control head between plate, and the length of control message only need be set to the minimum message length of Flow Control message between plate between this plate.
Fig. 4 is a method flow schematic diagram of realizing the transfer capability detection of dynamic in the embodiment of the invention.This method can be applicable in the distributed route system, and as shown in Figure 4, this method comprises:
Step 400 is provided with upper limit threshold BD_USED_HIGH and lower threshold BD_USED_LOW; An initial value is set is 0 variable BD_used_num, be used to represent the current BD quantity of having used state; An initial value is set is 0 variable Busy_send, be used for expression and whether sent the CBUSY message recently.
Step 402, whenever CPU handles message between a plate, after promptly discharging a BD, the pairing BD of memory headroom that this CPU stores message between this plate is set to idle condition and BD_used_num is subtracted 1, judge that simultaneously whether BD_used_num is smaller or equal to BD_USED_LOW, if and Busy_send be that 1 expression had sent the CBUSY message recently, then generate the FPGA that plate inner control message n_CBUSY sends to this CPU place exit plate, Busy_send is set to 0 simultaneously, and expression did not send plate inner control message CBUSY recently.
Step 404, if the FPGA of incoming interface plate receives control message FBUSY between plate, then this incoming interface buttress is according to the source plate ID that carries in the message, promptly the ID of outgoing interface plate stops to send message or reducing the message flow that sends to the outgoing interface plate to corresponding outgoing interface plate; If the FPGA of incoming interface plate receives control message n_FBUSY message between plate, then this incoming interface plate keeps the message flow that sends when the corresponding outgoing interface of forward direction or increases the message flow that sends to the outgoing interface plate.
So far, this flow process finishes.
Need to prove that step 401 in the above-mentioned flow process and step 402 are the processing procedure that circulation is repeatedly carried out.
In the practical application, preferably, upper limit threshold BD_USED_HIGH should smaller or equal to total BD quantity and plate inner control message transmissions, and plate between control message transmissions in total time, be that message arrives the poor of the pairing BD quantity in required maximum memory space in time of opposite end, be not enough to be stored in the message that receives in the above-mentioned time and cause packet loss with the idle BD that avoids outgoing interface plate CPU side; Lower threshold BD_USED_LOW then should arrive the maximum message segment quantity that CPU can handle in time of opposite end more than or equal to message, and is all idle and cause the outgoing interface plate CPU free time with the BD that avoids outgoing interface plate CPU side.
Suppose that the minimum message length that CPU mails to this plate FPGA is 16 bytes, then message arrives the time of opposite end, and promptly handle kernel and produce CBUSY or n_CBUSY message and receive that to FPGA the time that needs mainly comprises from CPU: time-delay of CPU Interrupt Process (about 1000ns) and interface delay time (16 * 8/10=12.8ns).
The time that FPGA processing CBUSY or n_CBUSY message need is equivalent to the time-delay (about 300ns) of a minimum data message in the FPGA inter-process.
As seen, plate inner control message transfer time is 1000+12.8+300+102.4=1415.2ns.
The minimum message length of supposing between plate the control message is 64 bytes, and then the time-delay that control message FBUSY or n_FBUSY transmit between outgoing interface plate and incoming interface plate between plate comprises: the interface time-delay of two physical layer interfaces such as SPI4 (2 * 64 * 8/10=102.4ns) and switching network inherent delay (about 2000ns).
Incoming interface plate FPGA is to the about 100ns of processing time-delay of control message FBUSY or n_FBUSY between plate.
As seen, the control message transfer time is between plate: 2000+100=2100ns.
Like this, plate inner control message transmissions, and plate between control message transmissions total time be: 1000+12.8+300+102.4+2000+100=3515.2ns.
As described in above-mentioned flow process, outgoing interface plate CPU side reach default upper limit threshold BD_USED_HIGH with BD quantity after, to be sent control message FBUSY between the plate of expressing interface board CPU disposal ability deficiency by the FPGA of outgoing interface plate to corresponding incoming interface plate, the transmission of this message between outgoing interface plate and incoming interface plate needs the time of about 3500ns.Under the worst case, this 3500ns in the time outgoing interface CPU always with maximum rate (10Gbps) packet receiving and do not deal with, then will receive the flow of 3500 * 10/8=4375 byte at most, message all is the minimum message of 64 bytes between the plate of supposing to receive, then total message number of receiving in the time at this 3500ns is 68, thereby need guarantee that idle BD number should be greater than 68 when outgoing interface plate CPU transmission board inner control message CBUSY.Therefore, the setting of BD_USED_HIGH threshold value should be satisfied: BD_USED_HIGH≤BD sum-68.
Equally, outgoing interface plate CPU side reach default lower threshold BD_USED_LOW with BD quantity after, to send the FBUSY message of expressing interface board CPU disposal ability deficiency to corresponding incoming interface plate by the FPGA of outgoing interface plate, this message transmits the time that needs about 3500ns between plate; The most optimistic situation is, this 3500ns in the time CPU handle the message of this buffer memory with maximum processing capability (3Mpps) always, 3500ns * 3Mpps=10.5, promptly need to guarantee when the CPU of outgoing interface plate transmission board inner control message n_BUSY, should be greater than 11 with the BD number, otherwise might cause the waste of outgoing interface plate CPU ability.
More than be to realizing the detailed description of the method for transfer capability detection of dynamic in the embodiment of the invention.Again the device of realizing the transfer capability detection of dynamic in the embodiment of the invention is described below.
Realize the device of transfer capability detection of dynamic among the present invention, can be used as the outgoing interface in the distributed route system, this device comprises: internal memory and CPU.
Each memory headroom in the internal memory is corresponding different B D respectively.
SPI4 interface hardware among the CPU this message is stored in the pairing memory headroom of idle BD, and this BD is set to use state after receiving message; Processing kernel among the CPU is after the processing of finishing message, and the pairing BD of memory headroom that stores this message is set to idle condition.
Simultaneously, the processing kernel among the CPU is when the interruption that treatment S PI4 interface hardware produces, and also whether detection reaches default upper limit threshold with the BD sum of state; When reaching default upper limit threshold with the BD sum of state, determine the transfer capability deficiency of this CPU.The BD of the processing kernel correspondence among the CPU is set to after the idle condition, can also detect interface board CPU side and whether reduce to default lower threshold with the BD sum of state; When reducing to default lower threshold with the BD sum of state, determine that this CPU has enough transfer capabilitys.
In order to realize Flow Control, realize among the present invention that the device of transfer capability detection of dynamic can comprise FPGA.Like this, CPU can send the plate inner control message of this CPU transfer capability deficiency of expression to FPGA after determining its transfer capability deficiency, controls message by FPGA between the plate of outside this plate of incoming interface transmission expression CPU transfer capability deficiency of correspondence; CPU is after definite this CPU has enough transfer capabilitys, also can send this CPU of expression and transmit the plate inner control message that enough transfer capabilitys be arranged, send this plate of expression CPU and have to the outside incoming interface plate of correspondence by FPGA between the plate of enough transfer capabilitys and control message to FPGA.
Below, in conjunction with an embodiment with preferred construction said apparatus is further specified.
Fig. 5 is an apparatus structure schematic diagram of realizing the transfer capability detection of dynamic in the embodiment of the invention.As shown in Figure 5, this device can be used as the outgoing interface in the distributed route system, comprising: internal memory, CPU and FPGA.
Wherein, the corresponding different B D of each memory headroom difference in the internal memory.
CPU comprises the SPI4 interface hardware and handles kernel, comprises BD administrative unit and task processing unit and handle kernel.
The SPI4 interface hardware can comprise a FIFO, receives the message from FPGA, and the message that receives is stored in the memory headroom corresponding with idle BD in the internal memory, send interrupt requests to the BD administrative unit, and this BD is set to use state.
The BD administrative unit, know that according to the interrupt requests that the SPI4 interface hardware sends its message that receives has been stored in the memory headroom corresponding with idle BD in the internal memory, and after interface hardware was stored in the message that receives in the memory headroom corresponding with idle BD in the internal memory, whether detection reached default upper limit threshold with the BD sum of state; When reaching default upper limit threshold with the BD sum of state, determine the transfer capability deficiency of its place CPU; Finish the processing of message at task processing unit after, the pairing BD of memory headroom that stores this message is set to idle condition.
Task processing unit is handled and is transmitted the message that receives, and notifies the BD administrative unit after the processing of finishing message.
In order to realize Flow Control between plate, with packet loss between the plate of avoiding causing by overflowing of CPU, the BD administrative unit further sends the plate inner control message of this CPU transfer capability deficiency of expression to FPGA by the SPI4 interface after the transfer capability deficiency of determining its place CPU; FPGA controls message between the plate of the outside incoming interface transmission expression CPU transfer capability deficiency of correspondence.
Before sending the plate inner control message of its place of expression CPU transfer capability deficiency to FPGA, the BD administrative unit can judge whether to send to FPGA the plate inner control message of its place of described expression CPU transfer capability deficiency earlier, if no, send the plate inner control message of this CPU transfer capability deficiency of expression again to FPGA by the SPI4 interface.
Certainly, the BD of correspondence is set to after the idle condition, and the BD administrative unit can further detect interface board CPU side and whether reduce to default lower threshold with the BD sum of state; When the BD sum with state is reduced to default lower threshold; When reaching default lower threshold with the BD sum of state, determine that its place CPU has enough transfer capabilitys.
In order to realize Flow Control between plate, cause the transfer capability waste of CPU to avoid the CPU free time, after definite its place CPU had enough transfer capabilitys, the BD administrative unit can further send this CPU of expression by the SPI4 interface to FPGA and transmit the plate inner control message that enough transfer capabilitys are arranged; FPGA then controls message between the outside incoming interface plate of correspondence sends this CPU of expression and have the plate of enough transfer capabilitys.
Before the plate inner control message that sends expression CPU transfer capability deficiency to FPGA, the BD administrative unit can further judge whether to send the plate inner control message of representing this CPU transfer capability deficiency to FPGA, if no, send the plate inner control message that expression its place CPU has enough transfer capabilitys by the SPI4 interface to FPGA again.
As seen from the above-described embodiment, the state of each BD by surveying the CPU side can detect the current disposal ability of this CPU, thereby can obtain the transfer capability of this CPU.Like this, with each corresponding incoming interface of outgoing interface CPU transfer capability notice, determine that in order to each incoming interface self is to message flow that this outgoing interface sent, with Flow Control between effective realization plate, guarantee that the message flow sum of all corresponding incoming interfaces can not exceed the CPU transfer capability of outgoing interface, thereby avoid outgoing interface place packet loss, avoid the waste of switching network flow.
And, when the CPU side is less than some with the BD of state, also can notifies each corresponding incoming interface to increase the message total amount of transmission, thereby can avoid the waste of outgoing interface CPU transfer capability.
Below only be all to adopt BD mechanism to realize that it is example that management, store status to memory headroom is designated BD with CPU.In the practical application, CPU also can adopt other modes to realize management to memory headroom, and correspondingly, the store status sign also can realize by other modes.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. a method that realizes the transfer capability detection of dynamic is applied to it is characterized in that in the distributed route system, and for each memory headroom in the outgoing interface board memory is provided with corresponding store status sign respectively, this method comprises:
After outgoing interface plate CPU receives message, this message is stored in idle store status identifies in the pairing memory headroom, and this store status sign is set to use state; CPU is after the processing of finishing message, and the pairing store status sign of memory headroom of storing this message is set to idle condition;
Whether detection reaches default upper limit threshold with the store status sign sum of state;
When reaching default upper limit threshold with the store status of state sign sum, determine the transfer capability deficiency of this CPU.
2. the method for claim 1 is characterized in that, store status sign is set to after the state at every turn, carries out described detection and whether reaches default upper limit threshold with the store status sign of state is total.
3. method as claimed in claim 2 is characterized in that, after the transfer capability deficiency of determining this CPU, this method further comprises:
Send the plate inner control message of this CPU transfer capability deficiency of expression to the field programmable gate array FPGA of this CPU place outgoing interface plate;
The FPGA of this CPU place outgoing interface plate controls message between the plate of this CPU transfer capability deficiency of incoming interface plate transmission expression of correspondence.
4. method as claimed in claim 3 is characterized in that, before described FPGA to this CPU place outgoing interface plate sent the plate inner control message of this CPU transfer capability deficiency of expression, this method further comprised:
Judge whether to send to the FPGA of this CPU place outgoing interface plate the plate inner control message of this CPU transfer capability deficiency of described expression, if no, then carry out the described plate inner control message that sends this CPU transfer capability deficiency of expression to the FPGA of this CPU place outgoing interface plate.
5. method as claimed in claim 3 is characterized in that, after described incoming interface plate to correspondence sent and controls message between the plate of representing this CPU transfer capability deficiency, this method further comprised:
The incoming interface plate stops to send message or reducing the message flow that sends to described outgoing interface plate to described outgoing interface plate.
6. as any described method in the claim 1 to 5, it is characterized in that the store status sign of each correspondence is set to after the idle condition, this method further comprises:
Detect interface board CPU side and whether reduce to default lower threshold with the store status sign sum of state;
When reducing to default lower threshold with the store status sign sum of state, determine that this CPU has enough transfer capabilitys.
7. method as claimed in claim 6 is characterized in that, after definite this CPU had enough transfer capabilitys, this method further comprised:
Send this CPU of expression to the FPGA of this CPU place outgoing interface plate and transmit the plate inner control message that enough transfer capabilitys are arranged;
The FPGA of this CPU place outgoing interface plate sends this CPU of expression and has to the incoming interface plate of correspondence between the plate of enough transfer capabilitys and controls message.
8. method as claimed in claim 7 is characterized in that, before described FPGA to this CPU place outgoing interface plate sent and represents that this CPU forwarding has the plate inner control message of enough transfer capabilitys, this method further comprised:
Judge whether to send the plate inner control message of representing that this CPU transmits enough transfer capabilitys to the FPGA of this CPU place outgoing interface plate, if no, then carrying out described FPGA to this CPU place outgoing interface plate sent and represented that this CPU had the plate inner control message of enough transfer capabilitys.
9. method as claimed in claim 7 is characterized in that, described incoming interface plate to correspondence sends this CPU of expression and have between the plate of enough transfer capabilitys after the control message, and this method further comprises:
The incoming interface plate keeps the message flow that sends when the described outgoing interface plate of forward direction or increases the message flow that sends to described outgoing interface plate.
10. method as claimed in claim 6 is characterized in that, described upper limit threshold arrives the opposite end pairing store status sign in required maximum memory space quantity poor in the time smaller or equal to total store status sign sum and message;
Described lower threshold arrives the opposite end maximum message segment quantity that CPU can handle in the time more than or equal to message.
11. the method for claim 1 is characterized in that, described store status is designated buffer description BD.
12. a device of realizing the transfer capability detection of dynamic is used for the outgoing interface of distributed route system, it is characterized in that this device comprises: internal memory and CPU, wherein,
The respectively corresponding different storage states sign of each memory headroom in the described internal memory;
After described CPU receives message, this message is stored in idle store status identifies in the pairing memory headroom, and this store status sign is set to use state; After the processing of finishing message, the pairing store status sign of memory headroom of storing this message is set to idle condition;
Whether described CPU detection reaches default upper limit threshold with the store status sign sum of state; When reaching default upper limit threshold with the store status of state sign sum, determine the transfer capability deficiency of this CPU.
13. device as claimed in claim 12 is characterized in that, described CPU carries out described detection and whether reaches default upper limit threshold with the store status sign sum of state after the store status sign is set to state.
14. device as claimed in claim 13 is characterized in that, this device further comprises: on-site programmable gate array FPGA;
Described CPU further sends the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA after determining its transfer capability deficiency;
Described FPGA controls message between the plate of the described CPU transfer capability deficiency of outside incoming interface transmission expression of correspondence.
15. device as claimed in claim 14, it is characterized in that, described CPU sends before the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA, further judge whether to send to described FPGA the plate inner control message of this CPU transfer capability deficiency of described expression, if no, then carry out the described plate inner control message that sends this CPU transfer capability deficiency of expression to FPGA.
16. as claim 14 or 15 described devices, it is characterized in that, the store status sign of described CPU correspondence is set to after the idle condition, further detects interface board CPU side and whether reduces to default lower threshold with the store status sign sum of state; When reducing to default lower threshold with the store status sign sum of state, determine that this CPU has enough transfer capabilitys.
17. device as claimed in claim 16 is characterized in that,
Described CPU further sends this CPU of expression to described FPGA and transmits the plate inner control message that enough transfer capabilitys are arranged after definite this CPU has enough transfer capabilitys;
Described FPGA sends the described CPU of expression and has to the outside incoming interface plate of correspondence between the plate of enough transfer capabilitys and controls message.
18. device as claimed in claim 17, it is characterized in that, described CPU is before sending the plate inner control message of this CPU transfer capability deficiency of expression to described FPGA, further judge whether to send the plate inner control message of representing this CPU transfer capability deficiency to described FPGA, represent that this CPU has the plate inner control message of enough transfer capabilitys if no, then carry out described the transmission to described FPGA.
19. device as claimed in claim 16 is characterized in that,
Described upper limit threshold smaller or equal to total store status sign quantity and message arrive the opposite end in the time the pairing store status in required maximum memory space identify the poor of quantity;
Described lower threshold arrives the opposite end maximum message segment quantity that CPU can handle in the time more than or equal to message.
20. device as claimed in claim 12 is characterized in that, described store status is designated buffer description BD.
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