Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
  • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
  • G01N27/403—Cells and electrode assemblies
  • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
  • G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing

Definitions

• ISFET ISFET Transistor
• Integrated circuit fabrication generally consists of a series of process steps or stages, for example, photolithography, etch, strip, diffusion, ion implantation, deposition, and the like.
• Integrated circuits are typically made on or in a semiconductor substrate that is commonly known as a wafer.
• materials or layers are added, treated and/or patterned on or in the wafer to form the integrated circuits.
• a photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are typically transparent fused silica blanks covered with a pattern defined with a chrome metal absorbing film.
• a stepper passes light through the reticle, forming an image of the reticle pattern. The image is focused and reduced by a lens, and projected onto the surface of a silicon wafer that is coated with a photosensitive material called photoresist.
• the coated wafer After exposure in the stepper, the coated wafer is developed like photographic film, causing the photoresist to dissolve in certain areas according to the amount of light the areas received during exposure.
• the developed wafer is then exposed to acids or other chemicals. The acid etches away the silicon in the parts of the wafer that are no longer protected by the photoresist coating.
• the wafer is then cleaned, recoated with photoresist, then passed through the stepper again in a process that creates the circuit on the silicon layer by layer. The entire process is called photolithography.
• ISFET Ion-Sensitive field effect transistor
• a first disadvantage of the process of application of ion-selective membrane by the conventional methods is the routing of the masks to be cleaned to another installation, generally that of the mask manufacturer.
• the present invention provides a method and system for applying ion- selective membrane on Ion-Sensitive Field Effect Transistor (ISFET) surface without involving a mask step.
• ISFET Ion-Sensitive Field Effect Transistor
• retaining structure is applied as a protective layer and to define the gate window opening before the polymer cocktail is applied.
• multi-purpose ISFET devices are first prepared at wafer level using a standard Complementary Metal Oxide Semiconductor (CMOS) fabrication process up to Metal 1 bond pad and a gate window is opened for ion sensing purposes.
• CMOS Complementary Metal Oxide Semiconductor
• membrane cocktails and photo polymerization are optimized in order to achieve reproducible ion-selective ISFET sensor characteristics without using a mask.
• the system of applying ion-selective membrane on ISFET surface comprises of a retaining structure for protecting and defining a gate window opening area on a substrate and a micropipette for manually pippetting out polymer cocktail at the gate of the substrate.
• the system and method eliminates the use of mask and therefore does away with the disadvantages associated with the same.
• Figure 1 shows a method of applying an ion-selective membrane on ISFET surface as per an embodiment herein.
• Figure 2 shows a system for applying polymer membrane cocktails, as per an embodiment herein.
• Figure 3 shows a cross section of mask less photo-cured ion-selective membrane on ISFET surface, as an exemplary embodiment of the process of application of ion-selective membrane on ISFET surface as described herein.
• retaining structure is applied as a protective layer and to define the gate window opening prior to membrane cocktail application.
• multi-purpose ISFET devices are first prepared at wafer level using a standard Complementary Metal Oxide Semiconductor (CMOS) fabrication process up to Metal 1 bond pad and ISFET gate window is open for ion sensing purposes.
• CMOS Complementary Metal Oxide Semiconductor
• Figure 1 shows a method of applying an ion-selective membrane on ISFET surface as per an embodiment herein.
• the ion-selective membrane is applied without involving a mask step.
• the method includes optimizing 101 layouts of the ISFET devices.
• the method further includes fabricating 103 multipurpose ISFET devices at wafer level using a standard Complementary Metal Oxide Semiconductor (CMOS) process up to metal 1 bond pad.
• CMOS Complementary Metal Oxide Semiconductor
• a gate window is opened for ion sensing purposes.
• Applying 105 retaining structure after general cleaning steps is necessary to define the gate window opening area.
• the retaining structure also acts as a protective layer.
• the method further includes applying 107 polymer cocktail of ion-selective membrane by manually pipetting out the polymer cocktail on gate window opening and photo polymerization of ion-selective membrane.
• the method also includes completing 109 the cell with only ISFET gate window open to analyte.
• Figure 2 shows a system for applying (107 of figure 1) polymer membrane cocktail, as per an embodiment herein.
• Figure 2 shows a substrate 201, a micropipette 203, and a retaining structure 205.
• the micropipette 203 is operated manually to pipette out a polymer cocktail 207 at a gate 209 on the substrate 201.
• the polymer cocktail 207 forms an ion-selective membrane 211.
• the application of the ion-selective membrane 211 is mainly on the gate 209 window opening area only.
• the retaining structure 205 is used to define the gate 209 window opening area and to provide a protective layer.
• Figure 3 shows a cross section of mask less photo-cured ion-selective membrane on ISFET surface, as an exemplary embodiment of the process of application of ion-selective membrane on ISFET surface as described herein.
• Figure 3 shows PCB 301 in side view and top view. Connector 303 is also shown in figure 3.

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Citations (3)

• 2007
  • 2007-12-06 MY MYPI20072179A patent/MY179070A/en unknown
• 2008
  • 2008-12-03 WO PCT/MY2008/000172 patent/WO2009151309A1/en active Application Filing

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